Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC

Author

Wen, Ya-Nan ; Wu, Guan-Lin ; Chen, Sao-Jie ; Hu, Yu-Hen

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1240

Lastpage

1243

Abstract

In this paper, the authors propose a novel high-throughput, ASIC architecture to realize the context-adaptive variable-length decoder (CAVLC) of H.264/AVC baseline profile. The authors conduct a thorough analysis of inherent parallelism of the CAVLC algorithm and identify particular steps that will benefit from parallel computing. In particular, the authors adopt a bit-position VLC decoding approach to decode multiple symbols concurrently in a critical step in CAVLC. This modification leads to almost 40% reduction of clock cycles compared to a straight-forward implementation

Keywords

entropy codes; variable length codes; video coding; ASIC architecture; H.264/AVC; bit-position; context-adaptive variable-length decoder; entropy coding; multiple-symbol parallel CAVLC decoder; parallel computing; Acceleration; Application specific integrated circuits; Automatic voltage control; Clocks; Computer architecture; Decoding; Entropy coding; Image coding; Parallel processing; Table lookup; CAVLC; H.264; entropy coding; multiple-symbol; variable length coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342387

Filename

4145624