Low Power Combinational Multipliers using Data-driven Signal Gating

A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computations and thus reduce the switching activity and power consumption of combinational multipliers. The proposed technique can be equally well applied to signed and unsigned multiplications. At the same time, it imposes reasonable area and delay overhead on the circuit. The benchmark data is extracted from typical DSP applications to show the efficiency of the proposed technique in the domain of DSP computations in which the low power computing is of rapidly increasing importance. The results show an average of 26% percent reduction in the switching activity and 22% area and 27% delay overhead, compared to combinational multipliers without this technique