DocumentCode
2248464
Title
Operation Scheduling for False Loop Free Circuits
Author
Huang, Shih-Hsu ; Cheng, Chun-Hua
Author_Institution
Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li
fYear
2006
fDate
4-7 Dec. 2006
Firstpage
1619
Lastpage
1622
Abstract
If resource constraints are specified, the false loop free circuit must be built during the scheduling phase. Although the previous approach guarantees to have a false loop free circuit mapping, it does not attempt to minimize the number of control steps. In this paper, we present an effective approach to find a scheduled code, which not only guarantees to have a false loop free circuit mapping but also to minimize the number of control steps. The proposed approach can be easily incorporated into any of existing list scheduling like algorithm. Experimental data shows that the proposed approach achieves very good results in terms of the number of control steps
Keywords
combinational circuits; high level synthesis; scheduling; control steps; false loop free circuit mapping; high-level synthesis; list scheduling like algorithm; operation scheduling; resource constraints; scheduled code; Calculators; Circuit synthesis; Combinational circuits; Control system synthesis; Delay; Hardware; High level synthesis; Resource management; Scheduling algorithm; Timing; False Loop; High-Level Synthesis; Scheduling;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location
Singapore
Print_ISBN
1-4244-0387-1
Type
conf
DOI
10.1109/APCCAS.2006.342074
Filename
4145718
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