Efficient Hardware Implementation for H.264/AVC Motion Estimation

Author

Bojnordi, Mahdi Nazm ; Semsarzadeh, Mehdi ; Hashemi, Mahmoud Reza ; Fatemi, Omid

Author_Institution

Sch. of Electr. & Comput. Eng., Tehran Univ.

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1749

Lastpage

1752

Abstract

Variable block size motion estimation (VBSME) is adopted in H.264/AVC to improve the coding efficiency. However, supporting various block sizes significantly increases the complexity of both video encoding and decoding. In this paper a multi-level parallel architecture for H.264/AVC motion estimation is proposed. SIMD architecture is proposed for absolute differentiator and accumulator (ADA). Using the ADA as the main processing engine, a cost and performance SAD processor is proposed. Experimental results indicate that more than 100% performance improvement is achieved by the proposed architectures compared to the state-of-the-art architectures with similar resources

Keywords

block codes; coprocessors; motion estimation; parallel architectures; video coding; H.264 AVC; SAD processor; SIMD architecture; absolute differentiator and accumulator; coding efficiency; multilevel parallel architecture; processing engine; variable block size motion estimation; video decoding; video encoding; Automatic voltage control; Computer architecture; Costs; Encoding; Engines; Hardware; Motion estimation; Parallel architectures; Very large scale integration; Video compression; H.264/AVC; VBSME; parallel architecture;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342156

Filename

4145750