Application of Multi-ported CAM for Parallel Coding

Author

Kumaki, Takeshi ; Kouno, Yutaka ; Ishizaki, Masakatsu ; Koide, Tetsushi ; Mattausch, Hans Jurgen

Author_Institution

Res. Center for Nanodevices & Syst., Hiroshima Univ.

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1859

Lastpage

1862

Abstract

This paper presents a parallel coding architecture using a flexible multi-ported content addressable memory (CAM). A previously reported flexible multi-port content addressable memory (FMCAM) technology (Kumaki et al., 2004) is improved by additional schemes for a single search mode and counting value setting and enables the fast parallel coding operation. Evaluation results for Huffman encoding within the JPEG application show that the proposed architecture can reduce the required clock-cycle number by 93% is comparison to a conventional DSP. Furthermore, the performance per unit area, measured in MOPS/mm², can be improved by a factor 3.8 in comparison to a conventional DSP

Keywords

Huffman codes; content-addressable storage; digital signal processing chips; parallel architectures; video coding; Huffman encoding; JPEG application; SIMD; bit parallel block parallel; flexible multiport content addressable memory; multiported CAM; parallel coding; parallel processing; reduced clock-cycle; Arithmetic; Associative memory; CADCAM; Computer aided manufacturing; Encoding; Hardware; Huffman coding; Image coding; Parallel processing; Transform coding; Bit parallel block parallel; CAM; Categorization; Content addressable memory; Huffman coding; Multiport; Parallel processing; SIMD;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342201

Filename

4145777