On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence

Author

Chen, Song ; Yoshimura, Takeshi

Author_Institution

Graduate Sch. of IPS, Waseda Univ., Kitakyushu

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1867

Lastpage

1870

Abstract

3D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3D IC floorplanning. It is proved that the number of configuration of 3D floorplans is less than that of planar floorplans. Sequence pair is extended (P-SP) to represent 3D IC floorplans. A new solution perturbation method remove and insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method

Keywords

integrated circuit interconnections; integrated circuit layout; perturbation techniques; simulated annealing; 3D IC floorplan configurations; interconnect problem; perturbation method insertion; perturbation method remove; sequence pair; simulated annealing algorithm; solution perturbation method; Clustering algorithms; Delay effects; Perturbation methods; Simulated annealing; Stacking; Three-dimensional integrated circuits; Very large scale integration; 3-D; VLSI; floorplanning; sequence pair;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342203

Filename

4145779