DocumentCode
2249741
Title
VHDL and Verilog compared and contrasted-plus modeled example written in VHDL, Verilog and C
Author
Smith, Douglas J.
Author_Institution
VeriBest Inc., Huntsville, AL, USA
fYear
1996
fDate
3-7 Jun, 1996
Firstpage
771
Lastpage
776
Abstract
This tutorial is in two parts. The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their differences. The second part contains a worked example of a model that computes the greatest common divisor (GCD) of two numbers. The GCD is modeled at the algorithmic level in VHDL, Verilog and for comparison purposes, C. It is then shown modeled at the RTL in VHDL and Verilog
Keywords
hardware description languages; integrated circuit design; logic CAD; C; RTL; VHDL; Verilog; algorithmic level; greatest common divisor; Application specific integrated circuits; Business; Design automation; Electronic design automation and methodology; Field programmable gate arrays; Hardware design languages; Libraries; Permission; USA Councils;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference Proceedings 1996, 33rd
Conference_Location
Las Vegas, NV
ISSN
0738-100X
Print_ISBN
0-7803-3294-6
Type
conf
DOI
10.1109/DAC.1996.545676
Filename
545676
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