Global Interconnect Analysis and Optimization for Nanometer Scale VLSI

The width of an interconnect and its spacing to neighboring interconnects affect greatly the delay and power dissipation of the line. Increasing the line width simply can reduce the delay but increase the power dissipation for a single line. If the line spacing is also increased appropriately, the power dissipated due to increasing the line width can be offset, even the power dissipation decrease. However, this improvement in the delay and power dissipation will conflict to the bandwidth. Therefore, a novel and efficient delay-power-reciprocal bandwidth tradeoff formulation is developed to optimize the width and spacing of global interconnects with repeaters for various ITRS nodes