DocumentCode
2250592
Title
Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1)
Author
Lin, Su-Hon ; Sheu, Ming-hwa ; Lin, Jing-Shiun ; Sheu, Wen-Tsai
Author_Institution
Graduate Sch. of Eng. Sci. & Technol., National Yunlin Univ. of Sci. & Technol.
fYear
2006
fDate
4-7 Dec. 2006
Firstpage
2020
Lastpage
2023
Abstract
This paper presents a new 3-moduli set (2n-1, 2n +1, 22n+1) and its RNS reverse converter design. The proposed 3-moduli set supports 1) larger dynamic range and 2) shorter internal computing delay, comparing to the most popular modular set (2 n-1, 2n+1, 2n). Besides, to speed up residue to binary conversion, a low-cost hardware circuit is designed by only using two carry-save adders and one end around carry CLA (EACLA). Under the same dynamic range requirement, the proposed converter design is significantly more efficient than the latest design for modular set (2n-1, 2n+1, 2n) with respect to hardware cost and area-time product (AT). Based on UMC 0.18mum CMOS cell-based technology, the core area for 16-bit RNS reverse converter is only 1836mum2 and the working frequency is 388MHz
Keywords
CMOS logic circuits; VLSI; adders; carry logic; digital signal processing chips; 0.18 micron; 388 MHz; EACLA; RNS reverse converter; UMC CMOS cell-based technology; VLSI design; binary conversion; carry-save adders; end around carry; low-cost hardware circuit; residue number system; Adders; Arithmetic; CMOS technology; Cathode ray tubes; Costs; Delay; Dynamic range; Hardware; Signal processing algorithms; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location
Singapore
Print_ISBN
1-4244-0387-1
Type
conf
DOI
10.1109/APCCAS.2006.342285
Filename
4145816
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