Hot-carrier reliability enhancement via input reordering and transistor sizing

Author

Dasgupta, Aurobindo ; Karri, Ramesh

Author_Institution

Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA

fYear

1996

fDate

3-7 Jun, 1996

Firstpage

819

Lastpage

824

Abstract

Hot-carrier effects and electromigration are the two important failure mechanisms that significantly impact the long-term reliability of high-density VLSI ICs. In this paper, we present a probabilistic switch-level method for identifying the most susceptible hot-carrier MOSFETs and improving their hot-carrier reliability using two techniques: (i) reordering of inputs to logic gates, and (ii) selective MOSFET sizing. We also show that for a given circuit, the best design in terms of hot-carrier reliability does not necessarily coincide with the best design in terms of power consumption

Keywords

MOSFET; hot carriers; semiconductor device models; semiconductor device reliability; MOSFET; circuit design; failure; high-density VLSI IC; hot carrier reliability; input reordering; logic gates; power consumption; probabilistic switch-level model; transistor sizing; Circuits; Electromigration; Energy consumption; Failure analysis; Hot carrier effects; Hot carriers; Logic gates; MOSFETs; Probabilistic logic; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference Proceedings 1996, 33rd

Conference_Location

Las Vegas, NV

ISSN

0738-100X

Print_ISBN

0-7803-3294-6

Type

conf

DOI

10.1109/DAC.1996.545684

Filename

545684