Estimation of SNM in latches and subsequent formation of a 10T CNFET bitcell

Author

Garg, Isha ; Sharma, Parmanand

Author_Institution

BITS Pilani, Pilani, India

fYear

2013

fDate

10-11 Sept. 2013

Firstpage

Lastpage

Abstract

This paper discusses the Static Noise Margin (SNM) for various configurations of latches, including radiation hardened latches using Schmitt Triggers with CMOS and CNFET models both., using the Butterfly Curve method. A bitcell is proposed based on the latch with the highest SNM, and its readability and writeability is estimated via the N-Curve method. Comparisons are made between the proposed 10T CNFET biteell and the basic 6T CMOS bitcell.

Keywords

CMOS integrated circuits; carbon nanotube field effect transistors; flip-flops; integrated circuit noise; radiation hardening (electronics); trigger circuits; Butterfly Curve method; CMOS bitcell; CNFET bitcell; N-Curve method; Schmitt triggers; radiation hardened latches; readability; static noise margin; writeability; CMOS integrated circuits; CNTFETs; Electron tubes; Inverters; Latches; Noise; Radiation hardening (electronics); Butterfly Curve; CNFET vs CMOS margins; N-Curve; SNM; radiation hardened latches; readability and writeability of bitcell;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Solutions in Embedded Systems (WISES), 2013 Proceedings of the 11th Workshop on

Conference_Location

Pilsen

Type

conf

Filename

6664951

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2252219