Hardware of structured brain computer

Author

Ae, Tadashi ; Sakai, Keiichi ; Araki, Hiroyuki ; Honda, Naoya

Author_Institution

Fac. of Eng., Hiroshima Univ., Japan

Volume

3

fYear

1998

fDate

21-23 Apr 1998

Firstpage

533

Abstract

We have proposed a two-level architecture for brain computing, where two levels are introduced for processing of meta-symbol. At Level 1 a conventional pattern recognition is performed, where neural computation is included, and its output gives the meta-symbol which is a symbol enlarged from a symbol to a kind of pattern. At Level 2 an algorithm acquisition is made by using a state machine for abstract states (which is a meta-symbol expression). We are also developing the VLSI chips at each level for the structured brain computer (SBC) version 1.0. To explain SEC we introduce the brain computing and the artificial memory system as well as the hardware of SBC

Keywords

content-addressable storage; feedforward neural nets; finite state machines; learning (artificial intelligence); parallel architectures; pattern recognition; symbol manipulation; VLSI chips; abstract state transition; algorithm acquisition; feedforward neural networks; learning algorithm; memory system; meta-symbol processing; pattern recognition; state machine; structured brain computer; two-level architecture; Artificial neural networks; Biological neural networks; Brain modeling; Clocks; Computer architecture; Computer networks; Concurrent computing; Hardware; Pattern recognition; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Knowledge-Based Intelligent Electronic Systems, 1998. Proceedings KES '98. 1998 Second International Conference on

Conference_Location

Adelaide, SA

Print_ISBN

0-7803-4316-6

Type

conf

DOI

10.1109/KES.1998.726019

Filename

726019