An all-digital phase-locked loop with dynamic phase control for fast locking

An all-digital phase-locked loop (ADPLL) featuring a dynamic phase compensation to accomplish fast-locking is reported. When a frequency-hopping event occurs, the compensation scheme implemented in both frequency and phase domain facilitates agile frequency settling. The phase error is monitored by an auxiliary time-to-digital converter (TDC) to control the divider ratio which directly modulates the frequency of the digital-controlled oscillator (DCO) through an integral path with auto-controlled gain. An uneven-step time-to-digital TDC is implemented for low-power and small chip area consideration. The proposed ADPLL has been fabricated in a 0.18-Pm CMOS technology. With less than 5-Ps locking time, the measured rms jitter from a 2.49-GHz carrier is about 1.93 ps. The whole ADPLL occupies a chip area of 1.8 mm2 and dissipates 10.35 mA from a 1.8-V supply.