• DocumentCode
    2253502
  • Title

    Automatic microarchitectural pipelining

  • Author

    Galceran-Oms, Marc ; Cortadella, Jordi ; Bufistov, Dmitry ; Kishinevsky, Mike

  • Author_Institution
    Univ. Politec. de Catalunya, Barcelona, Spain
  • fYear
    2010
  • fDate
    8-12 March 2010
  • Firstpage
    961
  • Lastpage
    964
  • Abstract
    This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct transformations including conversion to a synchronous elastic form, early evaluation, inserting empty buffers, anti-tokens, and retiming. The design exploration is done by solving an optimization problem followed by simulation of solutions. The method is explained on a DLX microprocessor example. The impact of different microarchitectural parameters on the performance is analyzed.
  • Keywords
    optimisation; pipeline processing; DLX microprocessor; antitokens; automatic microarchitectural pipelining; early evaluation; inserting empty buffers; optimization problem; synchronous elastic form; Clocks; Counting circuits; Delay; Design automation; Design optimization; Microarchitecture; Pipeline processing; Protocols; Space exploration; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4244-7054-9
  • Type

    conf

  • DOI
    10.1109/DATE.2010.5456910
  • Filename
    5456910
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2253502