A shuffled message-passing decoding method for memory-based LDPC decoders

Author

Ueng, Yeong-Luh ; Yang, Chung-Jay ; Chen, Chun-Jung

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2009

fDate

24-27 May 2009

Firstpage

892

Lastpage

895

Abstract

The convergence speed of shuffled message passing decoding (MPD) is faster than that of standard two phase message passing (TPMP) decoding. Due to complex memory access and requirement of large storage space, the shuffled MPD is not suitable for hardware implementation especially for high-rate LDPC codes. In this paper, we propose a modified shuffled MPD which can achieve a similar convergence speed but with reduced complexity in memory access and storage space as compared to the conventional shuffled MPD. We implement a rate-5/6 LDPC decoder based on the proposed algorithm.

Keywords

computational complexity; decoding; parity check codes; complexity reduction; low density parity check codes; memory access; memory-based LDPC decoders; shuffled message-passing decoding method; storage space; two phase message passing decoding; Bit error rate; Code standards; Convergence; Hardware; Iterative decoding; Message passing; Parity check codes; Phase change materials; Scheduling; WiMAX; LDPC decoder; Shuffled; iterative decoding; low-density parity-check (LDPC) codes; message-passing decoding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5117900

Filename

5117900