Pipelined parallel multiplier implementation

Author

Stiles, Bryan W. ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

1993

fDate

1-3 Nov 1993

Firstpage

364

Abstract

Two´s complement pipelined array and Wallace/Dadda (1964, 1965) multipliers are designed using LSI Logic 1.0-micron array based logic devices. The overall complexity of the multipliers and delay per pipeline stage is compared for various operand bit lengths and pipeline stage sizes. In order to optimize complexity and delay, issues including fanout, individual gate size and delay, minimization of the number of bits passed between pipeline stages, and optimization of pipeline stage size are considered. Both scalar and vector modes of operation are optimized

Keywords

digital arithmetic; large scale integration; logic arrays; multiplying circuits; parallel architectures; pipeline arithmetic; 1.0 micron; LSI logic devices; Wallace/Dadda multipliers; complexity; delay; delay per pipeline stage; fanout; gate size; operand bit lengths; pipeline stage sizes; pipelined parallel multiplier; scalar operation mode; two´s complement pipelined array; vector operation mode; CMOS logic circuits; Delay; Hardware; Large scale integration; Logic arrays; Logic design; Logic devices; Optimization methods; Pipelines; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1993. 1993 Conference Record of The Twenty-Seventh Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-4120-7

Type

conf

DOI

10.1109/ACSSC.1993.342535

Filename

342535