• DocumentCode
    2254632
  • Title

    Cross-layer resilience challenges: Metrics and optimization

  • Author

    Mitra, Subhasish ; Brelsford, Kevin ; Sanda, Pia N.

  • Author_Institution
    Dept. of EE, Stanford Univ., Stanford, CA, USA
  • fYear
    2010
  • fDate
    8-12 March 2010
  • Firstpage
    1029
  • Lastpage
    1034
  • Abstract
    With increasing sources of disturbances in the underlying hardware, a key challenge in design of robust systems is to meet user expectations at required cost. Cross-layer resilience techniques, implemented across multiple layers of the system stack and designed to work together, can help system designers build effective robust systems at the desired cost point. This paper brings to the forefront two major cross-layer resilience challenges: 1. Quantification and validation of the effectiveness of a cross-layer resilience approach to robust system design in overcoming hardware reliability challenges. 2. Global optimization of a robust system design using cross-layer resilience techniques.
  • Keywords
    circuit optimisation; fault tolerance; integrated circuit reliability; logic design; cost point; cross-layer resilience challenge; cross-layer resilience quantification; cross-layer resilience technique; cross-layer resilience validation; global optimization; hardware reliability; robust system design; system stack; user expectation; Built-in self-test; Circuits; Cost function; Design optimization; Error correction; Hardware; Logic; Resilience; Robustness; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4244-7054-9
  • Type

    conf

  • DOI
    10.1109/DATE.2010.5456961
  • Filename
    5456961