A 14-b 32MS/s Pipelined ADC with novel fast-convergence comprehensive background calibration

This paper presents a comprehensive calibration engine for Pipelined ADCs. Linear, nonlinear, memory errors as well as errors due to the capacitor mismatch in a multi-bit DAC are all estimated and compensated for using background digital calibration techniques. The work also includes a novel approach for correcting nonlinear errors that reduces the digital complexity and enhances the convergence rate of the error estimation. Conventional background calibration techniques are very slow and need millions of iterations to converge. By digitally filtering the input signal during the error estimation procedure, this work demonstrates significant improvement in convergence rate. Implemented in 0.25 um CMOS process, the pipelined ADC consumes 75 mA from 2.5 V and occupies 2.8 mm² of active area Measurement results show that calibration significantly improved dynamic (SNDR, SFDR) as well as static (DNL, INL) performance of the ADC.