Deep levels in ion implanted field effect transistors on SiC

Silicon Carbide (SiC) is emerging as an important material for fabricating high power, high temperature and high frequency devices because it has high thermal conductivity, large saturation electron drift velocity, high electric breakdown field and excellent thermal stability. Ion implantation of donor and acceptor impurities into bulk SiC is an attractive method for making planar devices and it has been used to fabricate a variety of SiC based FETs in the past few years. However, the performance and reliability of these devices still remain a serious problem for industrial applications. This is due to channel/insulator or channel/substrate interface traps, which reduce the mobilities in MISFETs and MESFETs to values much lower than those measured in bulk material. Deep Level Transient Spectroscopy (DLTS) is an excellent way to evaluate these trap, but only a few studies have been done on the deep levels. In this work interface traps are studied in detail for two FET device structures: MISFET on p-type 6H-SiC and MESFET on semi-insulating (SI) bulk 4H-SiC. For MISFETs the traps at the gate insulator/semiconductor interface created during insulator deposition and for MESFETs, the traps at the channel/substrate interface introduced by the ion-implantation process are examined.