Comparison of two SRAM matrix leakage reduction techniques in 45nm technology

As a consequence of technology shrinking, leakage current has become a significant contributor to the overall power dissipation of embedded memories. In this paper, we compare design trade-offs of two leakage reduction techniques, namely the diode clamp scheme and the replica cell biasing scheme. We show how the two techniques compare using a 1V, 900MHz, 1k × 32b reference SRAM in 45nm technology with a data retention voltage of 0.5V, which employs no leakage reduction scheme. The performance comparison is presented over an operating temperature range of -40°C to +130°C. We show that the replica cell biasing scheme can achieve 85.9% reduction in leakage current with an estimated gate area overhead of 2.3% plus area of polysilicon resistors (per memory instance) together with a speed reduction of 34.5% under most leaking conditions. The figures are 84.8%, 2.2% and 23.7% respectively for the diode clamp scheme.