DocumentCode
2256327
Title
Process variations in sub-threshold SRAM cells in 65nm CMOS
Author
Moradi, Farshad ; Wisland, Dag ; Berg, Yngvar ; Aunet, Snorre ; Cao, Tuan Vu
Author_Institution
Nanoelectronic Group, Univ. of Oslo, Oslo, Norway
fYear
2010
fDate
19-22 Dec. 2010
Firstpage
371
Lastpage
374
Abstract
In this paper the effects of process variations on SRAM cell are investigated. The SNM (static noise margin) changes due to the threshold voltage variations, is discussed in details. In addition, the effect of NBTI in sub-threshold SRAM design is presented. Simulation results shows the effect of process variation including mismatches on SRAM cell. The SNM is degraded by 35% for higher temperatures and low supply voltage applications. Process variation effects on SRAM cells are included. STM 65nm models are used for simulations.
Keywords
CMOS memory circuits; SRAM chips; CMOS; NBTI; process variation; size 65 nm; static noise margin; sub-threshold SRAM cell; threshold voltage variation; CMOS integrated circuits; CMOS technology; MOS devices; Random access memory; Reliability; Variable speed drives;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics (ICM), 2010 International Conference on
Conference_Location
Cairo
Print_ISBN
978-1-61284-149-6
Type
conf
DOI
10.1109/ICM.2010.5696164
Filename
5696164
Link To Document