A 65 nm CMOS digital processor for multi-mode time interleaved high-pass ΣΔ A/D converters

Digital processing in Time Interleaved High-Pass Sigma-Delta (TIHPSigmaDelta) Analog to Digital Converter (ADC) remains a bottleneck to realize high performances data converters. This paper proposes a new digital filter architecture which use comb-filter cells. Comparing to existing solutions, our circuit reduces considerably complexity and power consumption of the digital post-filtering at the back end of the TIHPSigmaDelta. The proposed solution was validated and synthesized in a 1.2 V, 65 nm CMOS process using VHDL language. For a clock rate of 220 MHz, the evaluated power consumption and die area are 12 muW and 0.13 mm² respectively.