DocumentCode
2258186
Title
Measuring and compensating for process mismatch-induced, reference spurs in phase-locked loops using a sub-sampled DSP
Author
Zhuo, Gao ; Kesharwani, Divya ; Chiang, Patrick ; Weiwu, Hu
Author_Institution
Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China
fYear
2009
fDate
24-27 May 2009
Firstpage
1585
Lastpage
1588
Abstract
A DSP method based on sub-sampling followed by M-point FFT of the sub-sampled signal is used to reduce the phase-locked loop´s reference spur. To validate the system´s effectiveness a digital calibration loop in SIMULINK is designed. The results show that the reference spur can be improved by 22 dBc with a 1% residual current mismatch and a 1 nA net value of leakage current.
Keywords
calibration; digital signal processing chips; fast Fourier transforms; leakage currents; phase locked loops; signal sampling; M-point FFT; PLL reference spur reduction; SIMULINK; current 1 nA; digital calibration loop; digital signal processing; phase-locked loop; subsampled DSP method; subsampled signal; Charge pumps; Circuit optimization; Clocks; Digital signal processing; Leakage current; Phase frequency detector; Phase locked loops; Phase measurement; Tuning; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location
Taipei
Print_ISBN
978-1-4244-3827-3
Electronic_ISBN
978-1-4244-3828-0
Type
conf
DOI
10.1109/ISCAS.2009.5118073
Filename
5118073
Link To Document