Power supply noise suppression by optimizing on-die PDN impedance

Author

Kobayashi, Yoshiyuki ; Kobayashi, Ryota ; Mido, T. ; Kubo, Genki ; Otsuka, Hiroyuki ; Fujii, Hiromitsu ; Sudo, Toshio

Author_Institution

Shibaura Inst. of Technol., Tokyo, Japan

fYear

2012

fDate

10-12 Dec. 2012

Firstpage

1

Lastpage

4

Abstract

Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, effects of damping condition of the total PDN impedance on power supply noise have been studied by adding variable on-die RC circuit to the intrinsic on-die RC circuit in chip PDN. Two types of test chips were designed with different variable on-die PDN impedances. By varying the values of on-die RC circuit, the simulated waveforms of power supply noises for the two test chips have been changed from oscillatory region to damped regions.

Keywords

CMOS digital integrated circuits; distribution networks; integrated circuit design; integrated circuit noise; interference suppression; CMOS digital systems; antiresonance peaks; chip-package interaction; electromagnetic radiation; logic instability; on-die power distribution network impedance; power integrity design; power supply fluctuation; power supply noise suppression;

fLanguage

English

Publisher

ieee

Conference_Titel

CPMT Symposium Japan, 2012 2nd IEEE

Conference_Location

Kyoto

Print_ISBN

978-1-4673-2654-4

Type

conf

DOI

10.1109/ICSJ.2012.6523443

Filename

6523443