Low complexity hardware interleaver for MIMO-OFDM based wireless LAN

A low complexity hardware interleaver architecture is presented for MIMO-OFDM based wireless LAN e.g. 802.11n. Novelty of the presented architecture is twofold; 1) Flexibility to choose interleaver implementation with different modulation scheme and different size for different spatial streams in a multi antenna system, 2) Complexity to compute on the fly interleaver address is reduce by using recursion and is supported by mathematical formulation. The proposed interleaver architecture is implemented on 65 nm CMOS process and it consumes 0.035 mm² area. The proposed architecture supports high speed communication with maximum throughput of 900 Mbps at a clock rate of 225 MHz.