Error resilience of intra-die and inter-die communication with 3D spidergon STNoC

Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high performance integrated circuits wires become the performance bottleneck and we are shifting towards communication centric design paradigms. Networks-on-chip and stacked 3D integration are two emerging technologies that alleviate the performance difficulties of on-chip interconnects in nano-scale designs. In this paper we present a design-time configurable error correction scheme integrated at link-level in the 3D Spidergon STNoC on-chip communication platform. The proposed scheme detects errors and selectively corrects them on the fly, depending on the critical nature of the transmitted information, making thus the correction software controllable. Moreover, the proposed scheme can correct multiple error patterns by using interleaved single error correction codes, providing an increased level of reliability. The performance of the link and its cost in silicon and vertical wires are evaluated for various configurations.