VLSI implementation of pulse coded winner take all networks

A VLSI implementation of a pulse coded winner-take-all network is presented. The pulse coded winner-take-all network uses a single inhibition bus to implement lateral inhibition. One advantage of the pulse coded winner-take-all is that it has a wiring complexity of O(n). This is in contrast with the standard winner-take-all whose wiring complexity is of O(n²). The pulse coded version also has the advantage of preserving the relative magnitude of the winning neuron´s incoming signals. Experimental results are presented