A low power reconfigurable heterogeneous architecture for a mobile SDR system

The main challenge in designing a mobile wireless software defined radio (SDR) system is to provide a solution that has high flexibility, hardware-like throughput, low power consumption, in addition to ease of programmability. In this paper, the authors propose a new architecture for SDR that is based on a reconfigurable instruction cell array (RICA). The architecture targets the IEEE 802.11g standard that includes Viterbi decoding, which is a key performance bottleneck. One of the salient novel features in this architecture, compared to existing solutions, is adopting a multi processor frame segmentation scheme when implement the 802.11 physical layer of the above standard. The paper describes the architecture, the associated software design flow, and performance efficiency. We demonstrate that the architecture can achieve a raw data throughput of 30.6 Mbps for an 802.11g receiver at a core power of 8.1 mW.