Optimized 16×16 discrete cosine transform architecture for homogeneity-based H.264/AVC intra mode decision

Author

Souza, Renato ; Rosa, Leomar Da, Jr. ; Agostini, Luciano ; Porto, Roger

Author_Institution

GACI - Group of Archit. & Integrated Circuits, UFPel - Fed. Univ. of Pelotas, Pelotas, Brazil

fYear

2012

fDate

20-23 March 2012

Firstpage

1

Lastpage

6

Abstract

To have a better coding performance, H.264/AVC encoder should choose the best block size in terms of bit rate and distortion. This work presents an optimized hardware architecture for the H.264/AVC 16×16 DCT. This architecture calculates the 24 coefficients utilized in a related work for homogeneity-based H.264/AVC intra mode decision. It was specified in VHDL and synthesized to a Xilinx Virtex2-Pro FPGA. Synthesis results indicate that the proposed solution is capable to reach high processing rates, permitting to use it in a hardware architecture for fast mode decision.

Keywords

discrete cosine transforms; field programmable gate arrays; logic design; video coding; VHDL; Xilinx Virtex2-Pro FPGA; hardware architecture; homogeneity-based H.264/AVC intra mode decision; optimized 16×16 discrete cosine transform architecture; Computer architecture; Discrete cosine transforms; Encoding; Field programmable gate arrays; Hardware; Standards; 16×16 Discrete Cosine Transform; DCT; H.264/AVC; Mode Decision; Video Coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Programmable Logic (SPL), 2012 VIII Southern Conference on

Conference_Location

Bento Goncalves

Print_ISBN

978-1-4673-0184-8

Type

conf

DOI

10.1109/SPL.2012.6211789

Filename

6211789