DocumentCode
2261781
Title
Weighted pseudo-random BIST for n-detection of single stuck-at faults
Author
Yu, Chaowen ; Reddy, Sudhakar M. ; Pomeranz, Irith
Author_Institution
Dept. of ECE, Iowa Univ., IA, USA
fYear
2004
fDate
15-17 Nov. 2004
Firstpage
178
Lastpage
183
Abstract
Detecting single stuck-at faults more than once has been shown to be an effective way to achieve high defect coverage. Recently it was observed that the number of tests required to achieve n-detection of single-stuck-at faults using pseudo-random sources may increase as n.logn with increasing values of n. In this paper, we investigate weighted pseudo-random BIST for n-detection of single stuck-at faults. We propose a hardware efficient weighted pseudo-random test pattern generator. Experimental results show that the proposed test pattern generator achieves n-detection of single stuck-at faults with test set sizes growing linearly with n. The hardware overhead grows modestly with n.
Keywords
automatic test pattern generation; built-in self test; circuit analysis computing; fault diagnosis; integrated circuit testing; logic testing; hardware overhead; n-detection; pseudo-random test pattern generator; single stuck-at faults detection; weighted pseudo-random BIST; Built-in self-test; Chaos; Cities and towns; Counting circuits; Fault detection; Hardware; Manufacturing; Phase shifters; Test pattern generators; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2004. 13th Asian
ISSN
1081-7735
Print_ISBN
0-7695-2235-1
Type
conf
DOI
10.1109/ATS.2004.89
Filename
1376555
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