Designing variation-tolerance in mixed-signal components of a system-on-chip

Nanoscale system-on-chip (SoC) devices offer potential for higher performance and reduced power consumption at lower cost. However yield and reliability of mixed-signal components in such devices become serious issues due to process variability. In this paper, we discuss a novel variation-tolerant technique for non-linearity errors in self-correctable mixed-signal components. We propose a completely digital method of test and correction of digital-to-analog and analog-to-digital converters (DAC/ADC) using a digital signal processor (DSP) assumed to be available on the SoC. The added hardware includes a first-order sigma-delta ADC for measurement and a low-resolution dithering DAC for correction of output. The DSP handles test pattern generation (TPG) and output response analysis (ORA) and a third-order polynomial fitting algorithm is employed to characterize the nonlinearity error. Simulation results demonstrate a reduction in nonlinearity errors of converters from plusmn1.5LSB down to plusmn0.5LSB. Our technique can also be applied to other mixed-signal devices with digital control.