DocumentCode
2262219
Title
A Scalable built-in self-test/self-diagnosis architecture for 2D-mesh based chip multiprocessor systems
Author
Lin, Shu-Yen ; Hsu, Chan-Cheng ; Wu, An-Yeu Andy
Author_Institution
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2009
fDate
24-27 May 2009
Firstpage
2317
Lastpage
2320
Abstract
In this paper, we proposed a scalable built-in self-test/self-diagnosis architecture, surrounding test ring (STR), to detect and locate faulty FIFOs and faulty MUXs for 2D-mesh based CMP systems. Proposed STR supports 97.79% fault coverage in FIFOs and MUXs and tests with 388 ~ 2886 test cycles in different testing methods and mesh sizes.
Keywords
built-in self test; multiprocessing systems; 2D-mesh; FIFO; MUX; built-in self-test architecture; chip multiprocessor systems; self-diagnosis architecture; surrounding test ring; Automatic testing; Built-in self-test; CMOS technology; Circuit faults; Electric breakdown; Electronic equipment testing; Fault detection; Integrated circuit interconnections; Multiprocessing systems; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location
Taipei
Print_ISBN
978-1-4244-3827-3
Electronic_ISBN
978-1-4244-3828-0
Type
conf
DOI
10.1109/ISCAS.2009.5118263
Filename
5118263
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