The testability of a reconfigurable fault-tolerant system

Author

Barbour, Ahmed E.

Author_Institution

Dept. of Math. & Comput. Sci., Georgia Southern Univ., Statesboro, GA, USA

fYear

1993

fDate

16-18 Aug 1993

Firstpage

461

Abstract

The testability of a new form of dynamic redundancy technique which uses the reconfigurability property of a voting device, called a two-level error masking circuit, 2-EMC, is investigated. The block design concepts are used to construct the dynamic fault-tolerant system and to generate test patterns for the dynamic system. The on-line fault detection mechanism is incorporated with the system by using content addressable memory, CAM, which contains a fault dictionary of the dynamic system. The CAM facilitates the testing procedure of the dynamic system. The proposed design is found to be testable and a fast test patterns algorithm is given

Keywords

automatic testing; content-addressable storage; fault location; fault tolerant computing; logic testing; redundancy; CAM; content addressable memory; dynamic redundancy technique; fast test patterns algorithm; online fault detection mechanism; reconfigurable fault-tolerant system; testability; two-level error masking circuit; voting device; Associative memory; CADCAM; Circuit testing; Computer aided manufacturing; Electrical fault detection; Fault tolerant systems; Redundancy; System testing; Test pattern generators; Voting;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Conference_Location

Detroit, MI

Print_ISBN

0-7803-1760-2

Type

conf

DOI

10.1109/MWSCAS.1993.343021

Filename

343021