Nonlinear CA based scalable design of on-chip TPG for multiple cores

This paper reports an efficient design of test pattern generators (TPGs) for a chip having multiple cores. It is built around nonlinear cellular automata (CA) based pseudo-random pattern generator (PRPG). The modular and cascadable structure of proposed n-cell PRPG can be utilized to construct the (n+1)-cell PRPG without sacrificing the pseudo-randomness quality. The efficiency of such a scalable PRPG structure is demonstrated in designing the on-chip TPGs for a VLSI chip implementing multiple cores.