DocumentCode
2262523
Title
Max-testable class of sequential circuits having combinational test generation complexity
Author
Das, Debesh Kumar ; Inoue, Tomoo ; Chakraborty, Susanta ; Fujiwara, Hideo
Author_Institution
Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
fYear
2004
fDate
15-17 Nov. 2004
Firstpage
342
Lastpage
347
Abstract
The paper uses the concept of time expansion model (Innoue et al., 2000) to find the test generation for acyclic sequential circuits. It identifies a class of sequential circuits called as max-testable sequential circuits, where test generation can be obtained using a combinational test generator with the capability of detecting multiple faults on a kernel of combinational circuit. Any acyclic sequential circuit without hold registers belongs to this class. For the sequential circuits having hold registers, a subset of such circuits is found to be belonged to max-testable class. The paper also suggests an algorithm to find such class of circuits.
Keywords
automatic test pattern generation; circuit complexity; logic testing; sequential circuits; acyclic sequential circuits; combinational circuit kernel; combinational test generation complexity; combinational test generator; hold registers; max-testable class; max-testable sequential circuits; multiple fault detection; time expansion model; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Fault diagnosis; Kernel; Registers; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2004. 13th Asian
ISSN
1081-7735
Print_ISBN
0-7695-2235-1
Type
conf
DOI
10.1109/ATS.2004.57
Filename
1376582
Link To Document