DocumentCode
2263359
Title
A routing-driven mapping for cellular-architecture FPGAs
Author
Ramineni, N. ; Chrzanowska-Jeske, M.
Author_Institution
Dept. of Electr. Eng., Portland State Univ., OR, USA
fYear
1993
fDate
16-18 Aug 1993
Firstpage
308
Abstract
In this paper a new technique for mapping digital circuits to fine-grain cellular-architecture FPGAs are presented. We will discuss the tree structures obtained by a new logic synthesis method. Tree restructuring method for routing-driven technology mapping will be shown. Initial results obtained are encouraging to carry further work in this direction
Keywords
cellular arrays; circuit CAD; field programmable gate arrays; logic CAD; logic design; programmable logic arrays; cellular-architecture FPGAs; digital circuits; field programmable gate arrays; fine-grain cellular-architecture FPGAs; logic synthesis method; routing-driven mapping; routing-driven technology mapping; tree restructuring method; tree structures; Boolean functions; Circuit testing; Digital circuits; Field programmable gate arrays; Logic; Prototypes; Routing; Table lookup; Tree data structures; Utility programs;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location
Detroit, MI
Print_ISBN
0-7803-1760-2
Type
conf
DOI
10.1109/MWSCAS.1993.343068
Filename
343068
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