Modified SDF Architecture for Mixed DIF/DIT FFT

In this paper, we propose the modified single-path delay feedback (SDF) architecture for FFT implementation, which implements a mixed decimation-in-frequency (DIF) / decimation-in-time (DIT) FFT algorithm. Since final stage is computed as DIT FFT algorithm and other stages including input stage are computed as DIF FFT algorithm, both of input and output data occur in normal order and additional clocks for reordering input or output do not required. This architecture is applied for 64-point FFT and compared to Radix-4 DIF SDF and Radix-4 multi-path delay commutator (MDC) architecture in the context of throughput, latency and hardware complexity. As a result, the proposed architecture has the same throughput as that of Radix-4 SDF and Radix-4 MDC architecture, and reduces the latency and hardware complexity with some tradeoff in hardware complexity increase compare to original SDF.