Timing Recovery Modification for High-rate BPSK and QPSK Digital Demodulator

In this paper, we describe improvements of data timing synchronization algorithms, which are suitable for high speed BPSK/QPSK coherent demodulator. Timing error synchronizers are usually the most complicated subsystems in the demodulator, and they often limit application of the DSP hardware in the high-rate data transmission. This contribution is focused on feedback timing estimators, especially adapted timing error detectors, and shows modifications of widely used algorithms, that reach better detection characteristics and easy implementation in DSP.