DocumentCode
2264793
Title
Multi-bit parallel digital adder using a symmetric signed-digit numbers
Author
Cherri, Abdallah K. ; Shaout, Adnan K.
Author_Institution
Dept. of Electr. & Comput. Eng., Michigan Univ., Dearborn, MI, USA
fYear
1993
fDate
16-18 Aug 1993
Firstpage
859
Abstract
A new recoding truth-table (using redundant signed-digit numbers) with a symmetrical complemented relationship between input minterms and their corresponding output bits is developed. Multi-bit parallel digital circuits for both the recoding algorithm and the adder logical functions are realized using OR-AND and AND-OR realizations
Keywords
adders; integrated logic circuits; logic design; parallel processing; redundant number systems; AND-OR realization; OR-AND realization; adder logical functions; multi-bit parallel digital adder; recoding algorithm; recoding truth-table; redundant signed-digit numbers; symmetric signed-digit numbers; Adders; Arithmetic; Costs; Delay; Digital circuits; Hardware; Logic gates; Pipeline processing; Table lookup; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location
Detroit, MI
Print_ISBN
0-7803-1760-2
Type
conf
DOI
10.1109/MWSCAS.1993.343204
Filename
343204
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