DocumentCode
2265528
Title
On the use and performance of explicit communication primitives in cache-coherent multiprocessor systems
Author
Qin, Xiaohan ; Baer, Jean-Loup
Author_Institution
Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
fYear
1997
fDate
1-5 Feb 1997
Firstpage
182
Lastpage
193
Abstract
Recent developments in shared-memory multiprocessor systems advocate using off-the-shelf hardware to provide basic communication mechanisms and using software to implement cache coherence policies. The exposure of communication mechanisms to software opens many opportunities for enhancing application performance. In this paper we propose a set of communication primitives implemented on a communication co-processor that introduce a flavor of message passing and permit protocol optimization. To assess the overhead of the software implementation of the primitives and protocols, we compare a PRAM model, a hardware cache coherence scheme, a software scheme implementing only the basic cache coherence protocol, and an optimized software solution supporting the additional communication primitives and running with applications annotated with those primitives. With the parameters we chose for the communication processor, the overall memory system overhead of the basic software scheme is at least 50% higher than that of the hardware implementation. With the adequate insertion of the communication primitives, the optimized software solution has a performance comparable to that of the hardware scheme
Keywords
cache storage; memory protocols; message passing; performance evaluation; shared memory systems; PRAM model; application performance; cache coherence protocol; cache-coherent multiprocessor systems; communication mechanisms; explicit communication primitives; hardware cache coherence scheme; hardware implementation; message passing; performance; protocol optimization; shared-memory multiprocessor systems; Application software; Coherence; Communication system software; Coprocessors; Hardware; Message passing; Multiprocessing systems; Phase change random access memory; Protocols; Software performance;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Computer Architecture, 1997., Third International Symposium on
Conference_Location
San Antonio, TX
Print_ISBN
0-8186-7764-3
Type
conf
DOI
10.1109/HPCA.1997.569659
Filename
569659
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