Multi single-stage-shuffling for fast packet switching

Output buffering packet switches achieve the best throughput-delay performance, at the expense of high cost. In this paper, an output buffering fast packet switch, based on multilayering of single-stage interconnection networks, is described. The switch has less complexity than existing output buffering switches, is fair, and preserves cell sequencing. The switch performance is evaluated under both uniform and nonuniform traffic patterns, and is compared to other known switch architectures