Ultra low power full adder topologies

Author

Moradi, Farshad ; Wisland, Dag T. ; Mahmoodi, Hamid ; Aunet, Snorre ; Cao, Tuan Vu ; Peiravi, Ali

Author_Institution

Nanoelectron. Group, Univ. of Oslo, Oslo, Norway

fYear

2009

fDate

24-27 May 2009

Firstpage

3158

Lastpage

3161

Abstract

In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65 nm standard models are used for simulations.

Keywords

adders; logic gates; network topology; gate diffusion input technique; sense energy recovery full adder design; ultra low power full adder topologies; Adders; Circuit simulation; Circuit synthesis; Circuit topology; Clocks; Dynamic voltage scaling; Power dissipation; Power engineering and energy; Threshold voltage; Very large scale integration; Full adder; GDI; SERF; Subthreshold;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118473

Filename

5118473

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2266442