An assertion-based verification method for SystemC TLM

SystemC TLM library is the de facto standard for the transaction level modeling of the System-on-Chip designs. In this paper, we will propose an on-line assertion-based verification method which can be used in the transaction modeling of SystemC. The advantage of this method is that simple properties can be extracted from the transactions with complex structures. Assertions are built from these properties using Property Specification Language and evaluated during the simulation. The experiment results show that our method enrich the TLM library with ABV ability while incurring unnoticeable performance overhead to the simulation.