An automatic network generator for design verification of electronic packages

The design and development of a non-manhattan multi-layered layout extractor is discussed. The tool extracts a physical database in DXF format and generates a SPICE compatible deck after accounting for discontinuities like bends, vias etc. and transmisson line effects in interconnects. Algorithms for identifying discontinuities and multi-conductor transmission line systems (MTLs) are presented. A model library architecture which provides the electrical models of frequently encountered geometric structures is briefly discussed. Extraction time for a typical single chip package on various hardware platforms is reported. The circuit equivalent of a sample structure, as interpreted by the program, is presented. A graphical user interface which aids in manual decomposition and verification of the package is briefly discussed