DocumentCode
2268183
Title
An asynchronous algorithm for sequential circuit test generation on a network of workstations
Author
Sienicki, James ; Bushnell, Michael ; Agrawal, Prathima ; Agrawal, Vishwani
Author_Institution
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
fYear
1995
fDate
4-7 Jan 1995
Firstpage
36
Lastpage
41
Abstract
We present a distributed algorithm for automatic test generation for sequential circuits. Our system uses a network of workstations by partitioning the fault list. Multiple test generation processes are run on separate processors. Unlike a prior implementation, the communication of detected faults among processors is asynchronous, with all computers processing and broadcasting detected faults without synchronization. We thus accomplish a reduction in duplicated computation and a general improvement in the speedup as compared to the synchronized parallelization. Experimental results demonstrate superlinear speedups for some of the benchmark circuits. A mathematical model is presented to explain the speedups
Keywords
automatic test software; fault diagnosis; logic testing; parallel algorithms; sequential circuits; asynchronous algorithm; automatic test generation; distributed algorithm; fault list partitioning; mathematical model; multiple test generation processes; sequential circuit test generation; workstation network; Automatic testing; Circuit faults; Circuit testing; Distributed algorithms; Electrical fault detection; Fault detection; Partitioning algorithms; Sequential analysis; Sequential circuits; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1995., Proceedings of the 8th International Conference on
Conference_Location
New Delhi
ISSN
1063-9667
Print_ISBN
0-8186-6905-5
Type
conf
DOI
10.1109/ICVD.1995.512074
Filename
512074
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