Experimental demonstration of optical processor-memory interconnection

In this work, we experimentally demonstrated the feasibility and performance of an optically-connected processor-memory system. An emulated CPU with the on-chip memory controller was implemented on a high-speed FPGA evaluation board, which communicated with another SRAM module through independent Rocket IO transceivers connected by a 2.5Gb/s optical channel. Data integrity and error-free performance are verified with a sequence of SRAM write and read operations.