• DocumentCode
    2271542
  • Title

    A fast-locking phase-locked loop using CP control and gated VCO

  • Author

    I-Ting Lee ; Yun-Ta Tsai ; Shen-Iuan Liu

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2012
  • fDate
    23-25 April 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A fast-locking phase-locked loop (PLL) using a CP control and a gated voltage-controlled oscillator is presented. This PLL is fabricated in a 90nm CMOS technology. The measured locking time is 3.78us from 640MHz to 800MHz. This PLL consumes 3.8mW for a supply of 1.2V and the active area is 0.0135mm2.
  • Keywords
    CMOS integrated circuits; charge pump circuits; phase locked loops; voltage-controlled oscillators; CMOS technology; CP control; PLL; fast-locking phase-locked loop; frequency 640 MHz to 800 MHz; gated VCO; gated voltage-controlled oscillator; measured locking time; power 3.8 mW; size 90 nm; time 3.78 mus; voltage 1.2 V; Clocks; Phase frequency detector; Phase locked loops; Synchronization; Time frequency analysis; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    PENDING
  • Print_ISBN
    978-1-4577-2080-2
  • Type

    conf

  • DOI
    10.1109/VLSI-DAT.2012.6212601
  • Filename
    6212601
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2271542