• DocumentCode
    2272548
  • Title

    Transforming Distributed Acyclic Systems into Equivalent Uniprocessors under Preemptive and Non-Preemptive Scheduling

  • Author

    Jayachandran, Praveen ; Abdelzaher, Tarek

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Illinois at Urbana-Champaign, Urbana, IL
  • fYear
    2008
  • fDate
    2-4 July 2008
  • Firstpage
    233
  • Lastpage
    242
  • Abstract
    Many scientific disciplines provide composition primitives whereby overall properties of systems are composed from those of their components. Examples include rules for block diagram reduction in control theory and laws for computing equivalent circuit impedance in circuit theory. No general composition rules exist for real-time systems whereby a distributed system is transformed to an equivalent single stage analyzable using traditional uniprocessor schedulability analysis techniques. Towards such a theory, in this paper, we extend our previous result on pipeline delay composition for preemptive and non-preemptive scheduling to the general case of distributed acyclic systems. Acyclic systems are defined as those where the superposition of all task flows gives rise to a Directed Acyclic Graph (DAG). The new extended analysis provides a worst-case bound on the end-to-end delay of a job under both preemptive as well as non-preemptive scheduling, in the distributed system. A simple transformation is then shown of the distributed task system into an equivalent uniprocessor task-set analyzable using traditional uniprocessor schedulability analysis. Hence, using the transformation described in this paper, the wealth of theory available for uniprocessor schedulability analysis can be easily applied to a larger class of distributed systems.
  • Keywords
    directed graphs; processor scheduling; directed acyclic graph; distributed acyclic systems; distributed system; equivalent uniprocessors; nonpreemptive scheduling; pipeline delay composition; real-time systems; uniprocessor schedulability analysis; worst-case bound; Circuit theory; Computer science; Control theory; Delay; Equivalent circuits; Impedance; Performance analysis; Pipelines; Processor scheduling; Real time systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real-Time Systems, 2008. ECRTS '08. Euromicro Conference on
  • Conference_Location
    Prague
  • ISSN
    1068-3070
  • Print_ISBN
    978-0-7695-3298-1
  • Type

    conf

  • DOI
    10.1109/ECRTS.2008.31
  • Filename
    4573119