3D IC test scheduling using simulated annealing

Three-dimensional integrated circuits (3D ICs) have many advantages over traditional integrated circuits. Although 3D ICs have such advantages, there are many difficulties to be overcome. Testing for 3D ICs is regarded as the most difficult challenge. High power density in 3D ICs causes rising temperature, which may cause test yield loss. In this paper, we propose a thermal-aware test scheduling technique for 3D ICs. Our experimental results show that the maximum temperature in the test schedule of our proposed technique is under the temperature limit while the test length overhead is only 19%.