A fault model for VHDL descriptions at the register transfer level

Author

Riesgo, T. ; Uceda, J.

Author_Institution

Div. de Ingenieria Electron., Univ. Politecnica de Madrid, Spain

fYear

1996

fDate

16-20 Sep 1996

Firstpage

462

Lastpage

467

Abstract

This paper presents a fault model for VHDL descriptions at the register transfer level and its evaluation with respect to a logic level fault model (single-stuck-at). The proposed fault model may be used for early estimations of the fault coverage before the synthesis is made in the design process of an integrated circuit. The obtained results show a high correlation between the fault coverages achieved with the proposed fault model and logic fault models on a set of examples. The main contribution of this work is the proposal of a new fault model for VHD/RT descriptions and the demonstration of its usefulness for estimating the achieved fault coverage with a set of test vectors in design phases previous to synthesis

Keywords

fault diagnosis; hardware description languages; logic testing; VHD/RT descriptions; VHDL descriptions; design phases; fault coverage; fault model; logic fault models; logic level fault model; register transfer level; single-stuck-at fault; test vectors; Algorithm design and analysis; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit modeling; Integrated circuit synthesis; Logic gates; Logic testing; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European

Conference_Location

Geneva

Print_ISBN

0-8186-7573-X

Type

conf

DOI

10.1109/EURDAC.1996.558244

Filename

558244